1. Field of the Invention
The present invention relates to solid-state circuitry and, more particularly, to Metal Oxide Semiconductor (MOS) transistors used in logic circuits and memory circuits, modified with microscale and nanoscale electrostatically actuated mechanical relay switches.
2. Discussion of the Prior Art
Reducing the leakage current in extreme-scaled devices is a great challenge, especially while maintaining a 60 mV/decade current swing. Power consumption in logic circuits and memory circuits such as Static Random Access Memory (SRAM) limit the usefulness of the circuits. In devices such as battery-powered sensors and electronics where most of the transistors are turned off in sleep mode, the off-state leakage of transistors can determine the battery's lifetime and possibly the useful lifetime of the device when the battery cannot be replaced.
In applications such as body-embedded electronics or ultra-miniature sensors, the battery itself is very small and overhead of leakage can determine whether an application is viable. Even when the power is plentiful, leakage current can lead to circuit heating and limit the frequency at which microprocessors can be run. For example, in SRAM, the leakage current power overhead can increase the number of current buffers needed to drive memory rows and columns, increasing heat generation, and ultimately limit the amount of SRAM that can be used in a microcomputer's components such as cache memory.
A typical CMOS inverter configuration includes an NMOS transistor and a PMOS transistor; the source in the PMOS device is connected to a ground contact “GND” and a drain voltage level contact “VDD”. In an output state of “high”, the two transistors' drains sit at VDD, with the two gates at GND. In this case, the NMOS channel sees a drain-to-source voltage of VDD, while the PMOS has a zero drain-to-source voltage. In the ideal MOS case, the NMOS would not conduct any charge, but there is usually a leakage in the off-stage NMOS transistor. In the “output off” state, the PMOS will have VDD equal to VDS and will conduct a leakage current. Hence, in the inverter, the “off” state power consumption is dominated by leakage current of the transistor which is supposed to be “off”.
In addition to the source to drain leakage current described here, the source-to-bulk, and drain-to-bulk leakage currents also potentially exist in CMOS technologies. However, these sources of leakage have been largely eliminated in SOI (Silicon-on-Insulator) technologies, where the bulk silicon has been eliminated. Another source of leakage that occurs in CMOS transistors is from gate-to-source and gate-to-drain currents. Efforts to reduce this leakage have been recently attempted using suspended gate devices. For example, Abelé et al. reported steep current vs. voltage curves using a resonant suspended gate enhancement mode device (see: N. Abelé, etal., “Suspended-Gate MOSFET: bringing new MEMS functionality into solid state MOS transistor”, IEDM, 2005). In this case the gate is physically disconnected and can move on top of a surrogate gate. Similarly, a depletion mode device with a suspended gate has also been presented (see: Hei Kam, etal, “A New Nano-Electro-Mechanical Field Effect Transistor Design for Low Power Electronics”, IEDM, 2005). A particularly serious issue with this method is the potential deleterious effect on the reliability of the exposed silicon-silicon dioxide interface. The fluctuations of the turn-on voltages of the transistors as a function of environmental variables may be too high for the suspended gate modifications, and suspended gate techniques do not reduce the leakage currents that exist from source to drain which are likely to be higher than the gate to source or drain currents as transistors are scaled below 65 nm channel lengths.
There is a need, therefore, for a method and transistor architecture that is operable without power loss from junction to junction (e.g., source-drain) leakage current.